A phase-locked loop (PLL) is often utilized within clock generation and distribution systems of an integrated circuit. In general, a PLL generates an output signal having a phase that is matched to the phase of a reference signal. The PLL is typically implemented as a control loop with the output signal being used as a negative feedback signal to control the PLL. The PLL includes a phase detector that compares the reference clock signal to the feedback clock signal to determine whether the phases of the reference clock signal and the feedback clock signal are aligned.
In many PLLs, the phase detector will detect the rising edges of both signals to make this determination. Likewise, the control loop within the PLL generally moves only the rising edge of the output clock signal in order to achieve phase lock. At the same time, many existing duty cycle correction (DCC) circuits adjust both the rising and falling edges of a clock signal in order to achieve a desired duty cycle for the clock signal. Because the PLL and the DCC control loops both adjust the rising edge of the output clock signal, integrating a DCC within the control loop of a PLL can cause interference with the operation of the PLL.